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| LH538700A FEATURES * 1,048,576 words x 8 bit organization * Access time: 100 ns (MAX.) * Power consumption: Operating: 550 mW (MAX.) Standby: 550 W (MAX.) * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 400-mil TSOP (Type II) DESCRIPTION The LH538700A is an 8M-bit mask-programmable ROM organized as 1,048,576 x 8 bits. It is fabricated using silicon-gate CMOS process technology. 32-PIN DIP 32-PIN SOP PRELIMINARY CMOS 8M (1M x 8) MROM PIN CONNECTIONS TOP VIEW A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 538700A-1 Figure 1. Pin Connections for DIP and SOP Packages 32-PIN TSOP (Type II) TOP VIEW A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 NOTE: Reverse bend available on request. 538700A-2 Figure 2. Pin Connections for TSOP Package 1 LH538700A PRELIMINARY CMOS 8M MROM A19 1 A18 31 A17 30 A16 2 A15 3 A14 29 A13 28 A12 4 A11 25 A10 23 A9 A8 A7 A6 26 27 5 6 ADDRESS BUFFER A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 ADDRESS DECODER MEMORY MATRIX (1,048,576 x 8) COLUMN SELECTOR SENSE AMPLIFIER CE 22 CE BUFFER TIMING GENERATOR OUTPUT BUFFER OE 24 OE BUFFER 32 16 VCC GND 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 538700A-3 Figure 3. LH538700A Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A19 D0 - D7 CE Address input Data output Chip enable input OE VCC GND Output enable input Power supply (+5 V) Ground 2 CMOS 8M MROM PRELIMINARY LH538700A TRUTH TABLE CE OE DATA OUTPUT SUPPLY CURRENT H L L X H L High-Z High-Z Output Standby Operating Operating NOTE: X = H or L. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT Topr Tstg - 0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 0 to +70 - 65 to +150 V V V C C RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance VIL VIH VOL VOH | ILI | | ILO | ICC1 ICC2 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = - 400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 100 ns t RC = 1 s CE = V IH CE = V CC - 0.2 V f = 1 MHz T A = 25C -0.3 2.2 2.4 0.8 VCC + 0.3 0.4 10 10 100 90 3 100 10 10 V V V V A A mA mA mA A pF pF 1 2 2 NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3 LH538700A PRELIMINARY CMOS 8M MROM AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 100 100 100 50 5 40 40 ns ns ns ns ns ns ns 1 1 NOTE: 1. This is the time required for the output to become high-impedance. AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input/output reference level Output load condition 0.4 V to 2.6 V 10 ns 1.5 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC pin and the GND pin. tRC A0 - A19 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOH tOHZ tCHZ D 0 - D7 DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 538700A-4 Figure 4. Timing Diagram 4 CMOS 8M MROM PRELIMINARY LH538700A PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 41.30 [1.626] 40.70 [1.602] 16 0.30 [0.012] 0.20 [0.008] 0 TO 15 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 15.24 [0.600] TYP. DIMENSIONS IN MM [INCHES] 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 1.40 [0.055] 17 0.50 [0.020] 0.30 [0.012] 32 11.50 [0.453] 11.10 [0.437] 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 1 20.80 [0.819] 20.40 [0.803] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT DIMENSIONS IN MM [INCHES] 32SOP 32-pin, 525-mil SOP 5 LH538700A PRELIMINARY CMOS 8M MROM 32TSOP (Type II) (TSOP032-P-0400) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 32 17 10.40 [0.409] 12.30 [0.484] 10.00 [0.394] 11.30 [0.445] 11.00 [0.433] 10.60 [0.417] 1 21.20 [0.835] 20.80 [0.819] 16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.4375 [0.017] 0.20 [0.008] 0.00 [0.000] 0.15 [0.006] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP400 32-pin, 400-mil TSOP (Type II) ORDERING INFORMATION LH538700A Device Type X Package D N S SR 32-pin, 600-mil DIP (DIP032-P-0600) 32-pin, 525-mil SOP (SOP032-P-0525) 32-pin, 400-mil TSOP (Type II) (TSOP032-P-0400) 32-pin, 400-mil TSOP (Type II) Reverse bend (TSOP032-P-0400) CMOS 8M (1M x 8) Mask-Programmable ROM Example: LH538700AD (CMOS 8M (1M x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP) 538700A-5 6 |
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